1. Field of the Invention
The present invention relates, in general, to integrated circuit planarization processes, and, more particularly, to a chemical mechanical planarization (CMP) process for semiconductor wafers that provides reduced scratch density.
2. Statement of the Problem
Integrated circuits are manufactured by stacking multiple layers of metal, semiconductor, and dielectric materials on a top surface of a semiconductor substrate. Each of these layers may be patterned to create complex microelectronic circuitry. Planarization of each of the layers is an important limitation to the number of layers used to form the integrated circuit devices. Non-planar layers are difficult to pattern using conventional photo resist techniques because the focal length varies across the surface of the semiconductor wafer. It is also difficult to form subsequent films on top of a non-planar layer resulting in voids in the subsequent layer. Also, non-planar layers are difficult to completely remove during an etch process. A number of planarization processes have been developed and include chemical mechanical planarization (CMP).
The CMP process involves holding a thin wafer of semiconductor material against a rotating wetted polish pad surface under a controlled downward pressure. A polishing slurry such as a mixture of either a basic or acidic solution is used as a chemical etch component in combination with an abrasive material such as alumina or silica particles. A rotating polishing head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft, porous wetted pad material such as blown polyurethane.
Removal rate during a CMP process is controlled by the pressure applied, composition of the polishing slurry, and density of the polishing pad. Hard polishing pads remove material from the semiconductor wafer at a higher rate. Softer pads, in contrast, remove material at a slower rate. Similarly, the slurry composition, applied pressure, and rotational speed of the platen can be varied in known ways to control the removal rate.
CMP processes are typically carried out in more than one stage to maximize removal rate while at the same time providing an upper surface with low scratch density. CMP conditions that tend to have high removal rates, also tend to leave the polished surface in a degraded condition. CMP conditions with lower removal rates tend to provide good surface condition, but are not cost effective alternatives because of the long process time. The prior art has addressed this problem by providing two-stage polishing processes whereby the bulk of material is removed during a first stage with a high polishing rate. A second stage follows the first stage with a much slower polishing rate to improve the surface condition with little removal of material from the surface of the integrated circuit. Typically the initial stage is much longer in duration than is the second stage.
It has been found, however, that although the purpose of the second stage of the CMP process is to improve surface condition, it actually degrades surface condition by some standards. While surface roughness may be improved by the slow rate polishing stage, scratch density actually increases using the conventional short polishing cycle. What is needed is a CMP process providing high average removal rate, and good surface condition of the polished surface with low scratch density.